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cy7c65213 cy7c65213a usb-uart lp bridge controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-81011 rev. *m revised august 9, 2016 usb-uart lp bridge controller features usb 2.0 certified, full-speed (12 mbps) ? supports communication driver class (cdc), personal health care device class (phdc), and vendor-device class ? battery charger detection (bcd) compliant with usb battery charging specification rev. 1.2 (peripheral detect only) ? integrated usb termination resistors single-channel configurable uart interfaces ? supports 2-pin, 4-pin, 6- pin, 8-pin uart interface ? data rates up to 3 mbps ? 256 bytes for each transmit and receive buffer ? data format: ? 7 or 8 data bits ? 1 or 2 stop bits ? no parity, even, odd, mark, or space parity ? supports parity, overrun, and framing errors ? supports flow control using cts, rts, dtr, dsr ? supports uart break signal ? cy7c65213 supports single channel rs232/rs422 interfaces whereas cy7c65213a supports rs232/rs422/rs485 interfaces general-purpose input/o utput (gpio): 8 pins supports unique serial number feature for each device, which fixes the com port number perm anently when usb-uart lp bridge controller device plugs in configuration utility (windows) to configure the following: ? vendor id (vid), product id (pid), and product and manufacturer descriptors ? uart ? charger detection ? gpio driver support for vcom and dll ? windows 10: 32- and 64-bit versions ? windows 8.1: 32- and 64-bit versions ? windows 8: 32- and 64-bit versions ? windows 7: 32- and 64-bit versions ? windows vista: 32- and 64-bit versions ? windows xp: 32- and 64-bit versions ? windows ce ? mac os-x: 10.6, and later versions ? linux: kernel version 2.6.35 and later versions ? android: gingerbread and later versions 512-byte flash for storing configuration parameters clocking: integrated 48 -mhz clock oscillator usb suspend mode for low power supports bus-/self-powered configurations compatible with usb 2.0 and usb 3.0 host controllers operating voltage: 1.71 to 5.50 v operating temperature: ? commercial: 0 c to 70 c ? industrial: ?40 c to 85 c esd protection: 2.2-kv hbm rohs-compliant package ? 28-pin ssop (10 7.5 1.65 mm, 0.65-mm pitch) ? 32-pin qfn (5 5 1 mm, 0.5-mm pitch) ordering part number ? cy7c65213-28pvxi ? cy7c65213-32ltxi ? CY7C65213A-28PVXI ? cy7c65213a-32ltxi applications blood glucose meter battery-operated devices usb-to-uart cables enables usb connectivity in legacy peripherals with uart point-of-sale (pos) terminals industrial and t&m (test and measurement) devices usb compliant the usb-uart lp bridge controller (cy7c65213 and cy7c65213a) is fully compliant with the usb 2.0 specification, usb-if test-id (tid) 40860041. table 1. cy7c65213 and cy7c65213-a features comparison features cy7c65213 cy7c65213-a rs-485 support no yes
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 2 of 29 more information cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly and effectively integrate the device in to your design. for a comprehensive li st of resources, see the document usb-serial bridge controller product overview . overview: usb portfolio , usb roadmap usb 2.0 product selectors: usb-serial bridge controller , usb to uart controller (gen i) knowledge base articles: cypress offers a large number of usb knowledge base articles covering a broad range of topics, from basic to advanced level. recommended knowledge base articles for getting started with usb-serial bridge controller are: ? kba85909 ? key features of the cypress ? usb-serial bridge controller ? kba85921 ? replacing ft232r with cy7c65213 usb-uart lp bridge controller ? kba85920 ? usb-uart and usb-serial ? kba85913 ? voltage supply range for usb-serial ? kba89355 ? usb serial cypress default vid and pid ? kba92641 ? usb-serial bridge controller managing i/os using api ? kba92442 ? non-standard baud rates in usb-serial bridge controllers ? kba91366 ? binding a usb-serial device to a microsoft ? cdc driver ? kba92551 ? testing a usb-serial bridge controller configured as usb-uart with linux ? for a complete list of knowledge base articles, click here . code examples: usb full-speed development kits: ? cyusbs232 , cypress usb-uart lp reference design kit ? cyusbs234 , cypress usb-serial (single channel) development kit ? cyusbs236 , cypress usb-serial (dual channel) development kit models: ibis cypress usb-uart lp reference design kit the cypress usb-uart lp reference design kit is a complete development resource. it provides a platform to develop and test custom projects. the development kit contains collateral materials for the firmware, hardware, and software aspects of a design.
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 3 of 29 contents block diagram ? cy7c65213/cy7 c65213a......... ........... 4 functional overview ........................................................ 4 usb and charger detect............................................. 4 serial communication ................................................. 4 gpio interface ............................................................ 5 memory ....................................................................... 5 system resources ...................................................... 5 suspend and resume................................................. 5 wakeup..................................................................... 5 software ...................................................................... 5 internal flash configuration .... .................................... 7 electrical specifications .................................................. 9 absolute maximum ratings........ ................................. 9 operating conditions................................................... 9 device-level specifications ........................................ 9 gpio ......................................................................... 10 reset ......................................................................... 11 uart......................................................................... 11 flash memory............................................................ 11 pin description ............................................................... 12 usb power configuration.............................................. 15 usb bus-powered configuration .............................. 15 self-powered configuration ...................................... 16 usb bus powered with variabl e i/o voltage ............ 17 application examples .................................................... 18 usb to rs232 converter .......................................... 18 usb to rs485 application ........................................ 19 battery operated bus-powered usb to mcu with battery charge detection ....................................................... 20 led interface ............................................................ 21 ordering information...................................................... 22 ordering code definitions ...... ................................... 22 package information ...................................................... 23 acronyms ........................................................................ 25 document conventions ................................................. 25 units of measure ....................................................... 25 document history page ................................................. 26 sales, solutions, and legal information ...................... 29 worldwide sales and design supp ort............. .......... 29 products .................................................................... 29 psoc? solutions ...................................................... 29 cypress developer community................................. 29 technical support .................. ................................... 29
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 4 of 29 block diagram ? cy7c65213/cy7c65213a functional overview cy7c65213/cy7c65213a is a fu lly integrated usb-to-uart bridge that provides a simple method to upgrade uart-based devices to usb with a minimal number of components. cy7c65213/cy7c65213a includes a usb 2.0 full-speed controller, a uart transceiver, an internal regulator, an internal oscillator, and a 512-byte flash in a 32-pin qfn and 28-pin ssop package. the internal flash is used to store custom-specific usb descriptors and gpio configurat ion. this is done in-system using a configuration utility t hat communicates over the usb interface. cypress provides royalty-free virtual com port (vcp) device drivers. the drivers allow the device to appear as a com port in pc applications. all uart signals, including handshaking and control signals, are implemented. usb and charger detect usb cy7c65213/cy7c65213a has a built-in usb 2 . 0 full-speed transceiver. the transceiver incorporates an internal usb series termination resistor on the usb data lines and a 1.5-k ? pull - up resistor on the usbdp. charger detection cy7c65213/cy7c65213a supports bcd for peripheral detect only and complies with the usb battery charging specification, rev . 1.2 . it supports the following charging ports: standard downstream port (sdp ): allows the system to draw up to 500-ma current from the host charging downstream port (cdp ): allows the system to draw up to 1.5-a current from the host dedicated charging port (dcp): allows the system to draw up to 1.5-a of current from the wall charger serial communication cy7c65213/cy7c65213a has a serial communication block (scb). each scb can implement uart interface. a 256-byte buffer is available in both the tx and rx lines. uart interface the uart interface provides asynchronous serial communication with other uart devices operating at speeds of up to 3 mbits/second. it supports 7 to 8 data bits, 1 to 2 stop bits, odd, even, mark, space, and no parity. the uart interface supports full-duplex communication with a signaling format compatible with the standard uart protocol. in cy7c65213, uart pins may be interfaced to industry standard rs232/rs422 transceivers wher eas in cy7c65213a these uart pins may be interfaced to rs232/rs422/rs485 transceivers. common uart functions, such as parity error and frame error, are supported. a 256-byte buffer is available in both tx and rx directions. cy7c65213/cy7c65213a supports baud rates ranging from 300 baud to 3 mbaud. uart baud rates can be set using the config uration utility. notes: parity error gets detected wh en uart transmitter device is configured for odd parity and uart receiver device is configured for even parity. frame error gets detected when uart transmitter device is configured for 7 bits data width and 1 stop bit, whereas uart receiver device is configured for 8 bit data width and 2 stop bits. uart flow control the cy7c65213/cy7c65213a device supports uart hardware flow control using control signal pairs, such as rts# (request to send) / cts# (clear to send) and dtr# (data terminal ready) / dsr# (data set ready). the following sections describe the flow control signals: cts# (input) / rts# (output) cts# can pause or resume data transmission over the uart interface. data transmission can be paused by de-asserting the cts signal and resumed by using cts# assertion. the pause and resume operation does not affect data integrity. with flow control enabled, receive buffer has a watermark level of 93%. after the data in the receive buffer reaches that level, the rts# signal is de-asserted, instructing the transmitting device to stop data transmission. the start of data consumption by the usb transceiver with integrated resistor voltage regulator internal 48 mhz osc gpio usbdp usbdm usb internal 32 khz osc reset uart 256 bytes rx buffer reset# vccio vccd 256 bytes tx buffer 512 bytes flash memory sie gpio3 gpio4 gpio5 gpio6 gpio7 txd dtr# rts# rxd ri# dsr# dcd# cts# vcc battery charger detection bcd gpio0 gpio1 gpio2
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 5 of 29 application reduces device data backlog. after it reaches the 75% watermark level, the rts# signal is asserted to resume data reception. dsr# (input) / dtr# (output) the dsr#/dtr# signals are used to establish a communication link with the uart. these signals complement each other in their functionality, similar to cts# and rts#. gpio interface cy7c65213/cy7c65213a has eigh t gpios. the configuration utility lets you configure the gpio pins. the configurable options are as follows: tristate: gpio tristated drive 1: output static 1 drive 0: output static 0 power#: power control for bus power designs txled#: drives led during usb transmit rxled#: drives led during usb receive tx or rx led#: drives led during usb transmit or receive. gpio can be configured to driv e led at 8-ma drive strength. sleep#: indicates usb suspend bcd0/1: two-pin output to indicate the type of usb charger busdetect: connects vbus pin for usb host detection memory cy7c65213/cy7c65213a has a 512-byte flash. flash is used to store usb parameters, such as vid/pid, serial number, and product and manufacturer descriptors, which can be programmed by the configuration utility. system resources power system cy7c65213/cy7c65213a supports the usb suspend mode to control power usage. cy7c65213/cy7c65213a operates in bus-powered or self-powered modes over a range of 3.15 v to 5.5 v. clock system cy7c65213/cy7c65213a has a fully integrated clock and does not require any external crystal. the clock system is responsible for providing clocks to all subsystems. internal 48-mhz oscillator the internal 48-mhz oscillator is the primary source of internal clocking in the cy7c65213/cy7c65213a device. internal 32-khz oscillator the internal 32-khz oscillator is the primary source of internal clocking in cy7c65213/cy7c65213a. reset the reset block ensures reliable power-on reset and brings the device back to the default known state. the reset# (active low) pin can be used by extern al devices to reset the cy7c65213/cy7c65213a. suspend and resume the cy7c65213/cy7c65213a dev ice asserts the sleep# pin when the usb bus goes into the suspend state. this helps to meet the stringent suspend curren t requirements of the usb 2.0 specification, while using the device in bus-powered mode. the device resumes from the suspend state under either of the following two conditions: 1. any activity is detected on the usb bus 2. the ri# (configured as wakeup) pin is asserted to generate remote wakeup to the host. wakeup the ri# (configured as wakeup) pin is used to generate the remote wakeup signal on the usb bus. the remote wakeup signal is sent only if the host enables this feature through the set_feature request. the device communicates support for the remote wakeup to the host through the configuration descriptor during the usb en umeration process. the cy7c65213 device allows enabling/disabling of the remote wakeup feature through the configuration utility. software cypress delivers a complete set of software drivers and a configuration utility to enabl e product configuration during system development. drivers for linux operating systems cypress provides a user mode usb driver library ( libcyusbserial.so ) that abstracts vendor commands for the uart interface and provides a simplified api interface for user applications. this library uses the standard open-source libusb library to enable usb communication. the cypress serial library supports the usb plug-and-play feature using the linux ?udev? mechanism. cy7c65213/cy7c65213a supports the standard usb cdc uart-class driver, which is bundled with the linux kernel. android support the cy7c65213/cy7c65213a solution also includes an android java class?cyusbserial.java?which exposes a set of interface functions to communicate with the device. drivers for mac osx cypress delivers a dynamically linked shared library ( cyusbserial.dylib ) based on libusb, which enables communication to the cy7c65213/cy7c65213a device. in addition, the device also supports the native mac osx cdc uart-class driver.
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 6 of 29 drivers for windows operating systems for windows operating systems (xp, vista, win7, win8 and win8.1), cypress delivers a user mode dynamically linked library?cyusbserial dll.this library abstracts the vendor-specific interface of the cy7c65213/cy7c65213a devices and provides convenient apis to the user. it provides interface apis for vendor-specific uart and class-specific apis for phdc. usb-uart lp bridge controller works with the windows-standard usb cdc uart class driver. a virtual com port driver?cyusbserial.sys? is also delivered, which implements the usb cdc class driver. the cypress windows drivers are windows hardware certification kit-compliant. these drivers are bound to device through wu (windows update) services. cypress drivers also support windows plug-and-play and power management and usb remote wake-up. windows-ce support the cy7c65213/cy7c65213a solution includes a cdc uart driver library for windows-ce platforms. device configuration utility (windows only) a windows-based configuration utili ty is available to configure device initialization parameters. this graphical user application provides an interactive interface to define boot parameters stored in the device flash. this utility allows the user to save a user-selected configuration to text or xml formats. it also allows users to load a selected configurations from text or xml formats. the configuration utility allows the following operations: view current device configuration select and configure uart, battery charging, and gpios configure usb vid, pid, and string descriptors save or load configuration you can download the free conf iguration utility and drivers at www.cypress.com/go/usbserial .
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 7 of 29 internal flash configuration the internal flash memory can be used to store configuration para meters as shown in the following table. a free configuration u tility is provided to configure the parameters listed in the table to meet application-specif ic requirements over a usb interface. the configuration utility can be downloaded at www.cypress.com/go/usbserial. table 2. internal flash configuration for both cy7c65213 and cy7c65213a parameter default value description usb configuration usb vendor id (vid) 0x04b4 default cypress vid. can be configured to customer vid usb product id (pid) 0x0003 default cypress pid. can be configured to customer pid manufacturer string cypress can be confi gured with any string up to 64 characters product string usb-uart lp can be configur ed with any string up to 64 characters serial string can be configured with any string up to 64 characters power mode bus powered can be configured to bus-powered or self-powered mode max current draw 100 ma can be configured to an y value from 0 to 500 ma. the configuration descriptor will be updated based on this. remote wakeup enabled can be disabled. remote wakeup is initiated by driving #ri low usb interface protocol cdc can be configured to function in cdc, phdc, or cypress vendor class vcc voltage is 3.3 v disabled this option should be checked if we need to bypass usb regulator in cy7c65213/cy7c65213a. vccio voltage is less than 2 v disabled this option should be checked if we need to bypass vccio regulator in cy7c65213/cy7c65213a. enable manufacturing interface enabled this option enables an additional vendor class manufacturing mode interface to reconfigure the cy7c65213/cy7c65213a. i/o level cmos can be configured to either cmos or lvttl. i/o mode fast can be configured to either fast or slow for emi considerations. baud rate 115200 can be configured in an editable drop-down combo box that lists the predefined, standard baud rates. you can also enter a specific baud rate in the combo box. type 8 pin this option is nor re-configurable. pre-configured to 8 pin type. data width 8 bits can be configured to either 7 bits or 8 bits. stop bits 1 bit can be configured to either 1 bit or 2 bits. parity none can be configured to either none, odd, even, mark, or space. invert rts disabled by selecting this option in usb serial configuration utili ty, the polarity of the rts line can be inverted. invert cts disabled by selecting this option in usb serial configuration utili ty, the polarity of the cts line can be inverted. invert dtr disabled by selecting this option in usb serial configuration utili ty, the polarity of the dtr line can be inverted. invert dsr disabled by selecting this option in usb serial configuration utili ty, the polarity of the dsr line can be inverted. invert dcd disabled by selecting this option in usb serial configuration utili ty, the polarity of the dcd line can be inverted. invert ri disabled by selecting this option in usb serial configuration utili ty, the polarity of the ri line can be inverted. drop packets on rx error disabled this parameter defines the behavior of the uart when an error is detected in the packet received (rx packet/byte). when this option is selected in usb serial configuration utility, the data packet/byte in the rx buffer is discarded.
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 8 of 29 disable cts and dsr pull-up during suspend enabled in an embedded system, this parameter can be se lected in usb serial configuration utility to reduce system current c onsumption dur ing suspend state. this parameter disables the cts and dsr pull-up resistors in the suspend state to meet usb 2.0 s pecification current requirements. bcd disabled charger detect is disabled by default. when bcd is enabled, three of the gpios must be configured for bcd. gpio configuration gpio0 txled# gpio can be configured as shown in table 13 on page 14 . gpio1 rxled# gpio2 tristate gpio3 power# gpio4 sleep# gpio5 busdetect gpio6 bcd0 gpio7 bcd1 table 2. internal flash configuration for both cy7c65213 and cy7c65213a (continued) parameter default value description
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 9 of 29 electrical specifications absolute maximum ratings exceeding maximum ratings [1] may shorten the useful life of the device. storage temperature .................................... ?55 c to +100 c ambient temperature with power supplied (industri al) ............................ ?40 c to +85 c supply voltage to ground potential v ccio ................................................................................ 6.0 v v cc ................................................................................... 6.0 v v ccd ............................................................................... 1.95 v v gpio .................................................................. v ccio + 0.5 v static discharge voltage esd protection levels: 2.2-kv hbm per jesd22-a114 latch-up current ........................................................... 140 ma maximum current per gpio ............................................ 25 ma operating conditions t a (ambient temperature under bias) industrial ........................................................ ?40 c to +85 c v cc supply voltage ........... .............. ............... .. 3.15 v to 5.25 v v ccio supply voltage ....................................... 1.71 v to 5.50 v v ccd supply voltage ........................................ 1.71 v to 1.89 v device-level specifications all specifications are valid for ?40 c ? t a ? 85 c, t j ? 100 c, and 1.71 v to 5.50 v, except where noted. table 3. dc specifications parameter description min typ max units details/conditions v cc v cc supply voltage 3.15 3.30 3.45 v set and configure correct voltage range using the configuration utility for v cc . 4.35 5.00 5.25 v v ccio v ccio supply voltage 1.71 1.80 1.89 v used to set i/o voltage. set and configure the correct voltage range using the configuration utility for v ccio . 2.0 3.3 5.5 v v ccd output voltage (for core logic) ? 1.80 ? v do not use this supply to drive the external device. ?1.71v ? vccio ?? 1.89 v: short v ccd pin with the v ccio pin ?v ccio > 2 v ? connect a 1-f capacitor (cefc) between the v ccd pin and ground cefc external regulator voltage bypass 1.00 1.30 1.60 f x5r ceramic or better i cc1 operating supply current ? 13 18 ma usb 2.0 fs, uart at 1-mbps single channel, no gpio switching at v cc = 5 v, v ccio = 5 v i cc2 usb suspend supply current ? 5 ? a does not include current through the pull-up resistor on usbdp in usb suspend mode, the d+ voltage can go up to a maximum of 3.8 v. table 4. ac specifications parameter description min typ max units details/conditions z out usb driver output impedance 28 ? 44 ? as cy7c65213 has internal termination resistors, external resistors are not required. twakeup wakeup from usb suspend mode ? 25 ? s note 1. usage above the absolute maximum conditions may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods of time may affect device reliability. when used below absolute maximum conditions but above normal operating conditions, the devi ce may not operate to specification.
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 10 of 29 gpio table 5. gpio dc specification parameter description min typ max units details/conditions v ih [2] input voltage high threshold 0.7 v ccio ? ? v cmos input v il input voltage low threshold ? ? 0.3 v ccio v cmos input v ih [2] lvttl input, v ccio < 2.7 v 0.7 v ccio ? ? v v il lvttl input, v ccio < 2.7 v ? ? 0.3 v ccio v v ih [2] lvttl input, v ccio > 2.7 v 2 ? ? v v il lvttl input, v ccio > 2.7 v ? ? 0.8 v v oh cmos output voltage high level v ccio ? 0.4 ? ? v i oh = 4 ma, v ccio = 5 v +/- 10% v oh cmos output voltage high level v ccio ? 0.6 ? ? v i oh = 4 ma, v ccio = 3.3 v +/- 10% v oh cmos output voltage high level v ccio ? 0.5 ? ? v i oh = 1 ma, v ccio = 1.8 v +/- 5% v ol cmos output voltage low level ? ? 0.4 v i ol = 8 ma, v ccio = 5 v +/- 10% v ol cmos output voltage low level ? ? 0.6 v i ol = 8 ma, v ccio = 3.3 v +/- 10% v ol cmos output voltage low level ? ? 0.6 v i ol = 4 ma, v ccio = 1.8 v +/- 5% rpullup pull-up resistor 3.5 5.6 8.5 k ? rpulldown pull-down resistor 3.5 5.6 8.5 k ? i il input leakage current (absolute value) ? ? 2 na 25 c, v ccio = 3.0 v c in input capacitance ? ? 7 pf vhysttl input hysteresis lvttl; v ccio > 2.7 v 25 40 ? mv vhyscmos input hysteresis cmos 0.05 v ccio ?? mv table 6. gpio ac specification parameter description min typ max units details/conditions t risefast1 rise time in fast mode 2 ? 12 ns v ccio = 3.3 v/ 5.5 v, cload = 25 pf t fallfast1 fall time in fast mode 2 ? 12 ns v ccio = 3.3 v/ 5.5 v, cload = 25 pf t riseslow1 rise time in slow mode 10 ? 60 ns v ccio = 3.3 v/ 5.5 v, cload = 25 pf t fallslow1 fall time in slow mode 10 ? 60 ns v ccio = 3.3 v/ 5.5 v, cload = 25 pf t risefast2 rise time in fast mode 2 ? 20 ns v ccio = 1.8 v, cload = 25 pf t fallfast2 fall time in fast mode 20 ? 100 ns v ccio = 1.8 v, cload = 25 pf t riseslow2 rise time in slow mode 2 ? 20 ns v ccio = 1.8 v, cload = 25 pf t fallslow2 fall time in slow mode 20 ? 100 ns v ccio = 1.8 v, cload = 25 pf note 2. v ih must not exceed v ccio + 0.2 v.
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 11 of 29 reset uart flash memory table 7. reset dc specifications parameter description min typ max units details/conditions v ih input voltage high threshold 0.7 v ccio ?? v v il input voltage low threshold ? ? 0.3 v ccio v rpullup pull-up resistor 3.5 5.6 8.5 k ? c in input capacitance ? 5 ? pf vhysxres input voltage hysteresis ? 100 ? mv table 8. reset ac specifications parameter description min typ max units details/conditions tresetwidth reset pulse width 1 ? ? s table 9. uart ac specifications parameter description min typ max units details/conditions f uart uart bit rate 0.3 ? 3,000 kbps table 10. flash memory specifications parameter description min typ max units details/conditions fend flash endurance 100k ? ? cycles fret flash retention. t a ? 85 c, 10 k program/erase cycles 10 ? ? years
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 12 of 29 pin description table 11. cy7c65213-28pvxi / cy7c65213a-2 8pvxi (28-pin ssop) pin description pin name type default description 1 txd output ? transmit asynchronous data output 2 dtr# output ? data terminal ready control output 3 rts# output ? request to send control output 4vcciopower ? supply to the device core and interface, 1.71 to 5.5 v 5 rxd input ? receiving asynchronous data input 6 ri# input ? ring indicator control input. can be configured as wake-up; low signal on this pin is used to wake up the usb host controller out of the suspend state 7 gnd power ? digital ground 8 gpio5 i/o tristate configurable gpio 9dsr#input ? data set ready control input 10 dcd# input ? data carrier detect control input 11 cts# input ? clear to send control input 12 gpio4 i/o sleep# configurable gpio 13 gpio2 i/o tristate configurable gpio 14 gpio3 i/o power# configurable gpio 15 usbdp usbio ? usb data signal plus, integrating termination resistor and a 1.5-k ? pull-up resistor 16 usbdm usbio ? usb data signal minus, integrating termination resistor 17 vccd power ? this pin is an output of an internal regulator and cannot drive external devices. decouple this pin to ground using 1 f capacitor when the vccio voltage is greater then 2 v. connec t this pin to vccio supply when the vccio voltage is less then 2 v. 18 gnd power ? digital ground 19 reset# xres ? chip reset, active low. can be left unconnected or have a pull-up resistor connected to vccio supply. 20 vcc power ? vbus supply voltage (usb) 3.15 to 5.25 v 21 gnd power ? digital ground 22 gpio1 i/o rxled# configurable gpio 23 gpio0 i/o txled# configurable gpio 24 nc ? ? no connect 25 nc ? ? no connect 26 dnu ? ? do not use 27 gpio6 i/o tristate configurable gpio 28 gpio7 i/o tristate configurable gpio txd dtr# rts# vccio rxd ri# gnd gpio5 dsr# dcd# cts# gpio4 gpio2 gpio3 usbdp usbdm vccd gnd reset# vcc gnd gpio1 gpio0 nc nc dnu gpio6 gpio7 cy7c65213 / cy7c65213a -28 pvxi top view txd dtr# rts# vccio rxd ri# gnd gpio5 dsr# dcd# cts# gpio4 gpio2 gpio3 usbdp usbdm vccd gnd reset# vcc gnd gpio1 gpio0 nc nc dnu gpio6 gpio7 cy7c65213/ cy7c65213a -28 pvxi bottom view
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 13 of 29 table 12. cy7c65213-32ltxi / cy7c65213a-32ltxi (32-pin qfn) pin description [3, 4] pin name type default description 1 vccio power ? supply to the device core and interface, 1.71 to 5.5 v 2 rxd input ? receiving asynchronous data input 3 ri# input ? ring indicator control input. can be configured as wake-up; low signal on this pin is used to wake up the usb host controller out of the suspend state 4 gnd power ? digital ground 5 gpio5 i/o tristate configurable gpio. see ta b l e 1 3 . 6 dsr# input ? data set ready control input 7 dcd# input ? data carrier detect control input 8 cts# input ? clear to send control input 9 gpio4 i/o sleep# configurable gpio. see ta b l e 1 3 . 10 gpio2 i/o tristate configurable gpio. see ta b l e 1 3 . 11 gpio3 i/o power# configurable gpio. see ta b l e 1 3 . 12 gpio6 i/o tristate configurable gpio. see ta b l e 1 3 . 13 gpio7 i/o tristate configurable gpio. see ta b l e 1 3 . 14 usbdp usbio ? usb data signal plus, integrating termination resistor and a 1.5-k ? pull-up resistor 15 usbdm usbio ? usb data signal minus, integrating termination resistor 16 vccd power ? this pin is an output of an internal regulator and cannot drive external devices. decouple this pin to ground using 1 f capacitor when the vccio voltage is greater then 2 v. connect this pin to vccio supply when the vccio voltage is less then 2 v. 17 gnd power ? digital ground 18 reset# xres ? chip reset, active low. can be left unconnected or have a pull-up resistor connected to vccio supply. 19 vcc power ? supply voltage (usb) 3.15 to 5.25 v 20 gnd power ? digital ground 21 gpio1 i/o rxled# configurable gpio. see ta b l e 1 3 . 22 gpio0 i/o txled# configurable gpio. see ta b l e 1 3 . 23 dnu ? ? do not use 24 agnd power ? analog ground cy7c65213 / cy7c65213a -32qfn top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 30 29 28 27 26 25 32 23 22 21 20 19 18 17 24 vccio rxd ri# gnd gpio5 dsr# dcd# cts# agnd dnu gpio0 gpio1 gnd vcc reset# gnd gpio4 gpio2 gpio3 gpio6 gpio7 usbdp usbdm vccd rts# dtr# txd dnu dnu dnu dnu dnu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 30 29 28 27 26 25 32 23 22 21 20 19 18 17 24 vccio rxd ri# gnd gpio5 dsr# dcd# cts# agnd dnu gpio0 gpio1 gnd vcc reset# gnd gpio4 gpio2 gpio3 gpio6 gpio7 usbdp usbdm vccd rts# dtr# txd dnu dnu dnu dnu dnu cy7c65213 / cy7c65213a -32qfn bottom view notes 3. all active low signals for the signal nam e are indicated by a # in this document. 4. any pin acting as an input pi n should not be left unconnected.
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 14 of 29 25 dnu ? ? do not use 26 dnu ? ? do not use 27 dnu ? ? do not use 28 dnu ? ? do not use 29 dnu ? ? do not use 30 txd output ? transmit asynchronous data output 31 dtr# output ? data terminal ready control output 32 rts# output ? request to send control output table 12. cy7c65213-32ltxi / cy7c65213a-32ltxi (32-pin qfn) pin description (continued) [3, 4] pin name type default description table 13. gpio configuration the following signal options can be configured on the gpio pins using a cypress-provided config uration utility, which you can download at www.cypress.com gpio configuration option description tristate i/o tristated [5] drive 1 output static 1 drive 0 output static 0 power# this output is used to control power to an exte rnal logic through a switch to cut off power prior to usb configuration and during usb suspend. 0 - usb device in configured state 1 - usb device in unconfigured state or during usb suspend mode txled# drives led during usb transmit rxled# drives led during usb receive tx and rx led# drives led during usb transmit and receive sleep# when low indicates usb suspend bcd0 configurable battery charger detect pins to indi cate the type of usb charger (sdp, cdp, or dcp) configuration example: 00 - draw up to 100 ma (unconfigured state) 01 - sdp (up to 500 ma) 10 - cdp/dcp (up to 1.5 a) 11 - suspend (up to 2.5 ma) this truth table can be configur ed using a configuration utility bcd1 busdetect vbus detect ion. connect vbus to this pin for vbus detection when using the bcd feature [6] . notes 5. any gpio, configured as ?input? should either be pulled high or low. a floating input pin (tristate) has an indeterminate vol tage level that can cause excess internal current consumption. a 10 k ? pull-up or pull-down resistor is recommended on each of the input pin. 6. when vbus = vccio, connect vbus to busdetection with a 10-k series resistor when vbus > vccio, connect vbus to busdetection via the resi stor divider network. select r1 and r2 values as follows: r1 10 k r2 / (r1 + r2) = vccio/vbus
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 15 of 29 usb power configuration the following section describes possible usb power configurations for the cy7c65213/cy7c65213a. refer to the pin description on page 12 for signal details. usb bus-powered configuration figure 1 shows an example of the cy7c65213/cy7c65213a in a bus-powered design. vbus is connected directly to the cy7c65213/cy7c65213a because it has an internal regulator. the usb bus-powered system must comply with the following requirements: 1. the system should not draw more than 100 ma prior to usb enumeration (unconfigured state). 2. the system should not draw more than 2.5 ma during usb suspend mode. 3. a high-power bus-powered syst em (can draw more than 100 ma when operational) must use power# (configured over gpio) to keep the current consumption below 100 ma prior to usb enumeration and 2.5 ma during usb suspend state. 4. the system should not draw more than 500 ma from the usb host. the configuration descriptor in the cy7c65213 flash should be updated to indicate bus power and the maximum current required by the system usi ng a configurat ion utility. figure 1. bus-powered configuration usb connector vbus d+ d- gnd vccio vccd 1 uf usb-uart lp cy7c65213 / cy7c65213a usbdp usbdm gnd reset# vcc txd rxd cts# rts# dtr# dsr# dcd# ri# gpio4 agnd gpio5 gpio6 gpio7 gpio0 gpio1 gpio2 gpio3 gnd gnd 4.7 uf 0.1 uf vcc vcc
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 16 of 29 self-powered configuration figure 2 shows an example of cy7c65213/cy7c65213a in a self-powered design. in this configuration: vcc is powered from usb vbus. vcc pin is also used to detect usb connection. vccio is powered from an external power supply. the vbus of the usb host is used to control the reset# pin of cy7c65213/cy7c65213a. when the vbus is present, reset to cy7c65213/cy7c65213a is de-asserted and the device enables an internal, 1.5-k ? pull-up resistor on usbdp. when the vbus is absent (the usb host is powered down), reset to cy7c65213/cy7c65213a is asserted, which causes the device to remove the 1.5-k ? pull-up resistor on usbdp. this ensures that no current flows from the usbdp to the usb host through a 1.5-k ? pull-up resistor, to comply with usb 2.0 specification. when reset is asserted to cy7c65213/cy7c65213a, all the i/o pins are tristated. using the configuration utility, the configuration descriptor in the cy7c65213/cy7c65213a flash should be updated to indicate that it is self-powered. figure 2. self-powered configuration usb connector vbus d+ d- gnd 10k 4.7k 1.71 to 1.89 v or 2.00 to 5.50 v vccio vccd 1 uf usb-uart lp cy7c65213 / cy7c65213a usbdp usbdm gnd reset# vcc txd rxd cts# rts# dtr# dsr# dcd# ri# gpio4 agnd gpio5 gpio6 gpio7 gpio0 gpio1 gpio2 gpio3 gnd gnd 4.7 uf 0.1 uf vccio 4.7 uf 0.1 uf vcc
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 17 of 29 usb bus powered with variable i/o voltage figure 3 shows the cy7c65213/cy7c65213a in a bus-powered system with variable i/o voltage . a low dropout (ldo) regulator is used to supply 1.8 v or 3.3 v (using a jumper switch) the input of which is 5 v from the vbus. another jumper switch is used to select vccio_1.8/3.3 v or 5 v from the vbus for the vccio pin of cy7c65213/cy7c65213a. this allows i/o voltage and supply to external logic to be se lected among 1.8 v, 3.3 v, or 5 v. the usb bus-powered system must comply with the following: 1. the system should not draw more than 100 ma prior to usb enumeration (unconfigured state). 2. the system should not draw more than 2.5 ma during usb suspend mode. 3. a hjgh-power bus-powered syst em (can draw more than 100 ma when operational) must use power# (configured over gpio) to keep the current consumption below 100 ma prior to usb enumeration and 2.5 ma during usb suspend state. figure 3. usb bus-powered with 1.8-v, 3.3-v, or 5-v variable i/o voltage [7] usb connector vbus d+ d- gnd vcc vccd 1 uf usb-uart lp cy7c65213 / cy7c65213a usbdp usbdm gnd reset# vccio txd rxd cts# rts# dtr# dsr# dcd# ri# gpio4 agnd gpio5 gpio6 gpio7 gpio0 gpio1 gpio2 gpio3 gnd gnd vin gnd shdn vout vadj jumper to select 1.8 v or 3.3 v vbus 0.1 uf tc 1070 1uf 1m 1 2 3 562k 2m 3.3 v 1.8 v 1 2 3 vccio_1.8/3.3 v vccio_1.8/3.3 v 1.8 v or 3.3 v or 5 v supply to external logic jumper to select 1.8 v/3.3 v or 5 v power switch 4.7 uf 0.1 uf vcc refer to note 6 4.7 uf 0.1 uf vccio note 7. 1.71 v ? v ccio ?? 1.89 v - short v ccd pin with v ccio pin; v ccio > 2 v - connect a 1-uf decoupling capacitor to the v ccd pin.
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 18 of 29 application examples the following section provides the cy7c 65213/cy7c65213a application examples. usb to rs232 converter cy7c65213/cy7c65213a can connect any embedded system, with a serial port, to a host pc through usb. cy7c65213/cy7c65213a enumerates as a com port on the host pc. the rs232 protocol follows bipolar signaling, that is, the output signal toggles between negative and positive polarity. the valid rs232 signal is either in the ?3- v to ?15-v range or in the +3-v to +15-v range, and the range between ?3 v to +3 v is invalid. in rs232, logic 1 is called ?mar k? and corresponds to a negative voltage range. logic 0 is called ?space? and corresponds to a positive voltage range. the rs232 level converter facilitates this polarity inversion and the voltage-level translation between the cy7c65213/cy7c65213a?s uart interface and rs232 signaling. in this application, as shown in figure 4 , gpio4 can be configured as sleep# or po wer# and connected to the shdn# pin of the rs232-level co nverter. default configuration of the gpio4 in the device is sl eep#. if gpio4 is configured as sleep#, a low on this pin indicates usb suspend; if gpio4 is configured as power#, a high on this pin indicates a state prior to usb configuration or usb suspend. gpio0 and gpio1 are configured as txled# and rxled# to drive two leds, indicating data transmit and receive, respectively. cy7c65213/cy7c65213a has been tested with maxim?s max3245 transceiver. a simple loop-back test can be performed on the usb-to-rs232 converter as follows: connect t he tx and rx lines of the rs232 interface with a jumper, transmit data to the converter through a com port communication terminal (such as hyper terminal or tera term), and verify if the same data is received. for detailed steps to test a usb-to-rs232 solution, refer to the section ?testing a usb to rs232 solution? in the application note an85514 . figure 4. usb to rs232 converter usb connector vbus d+ d- gnd vccio vccd 1 uf usb-uart lp cy7c65213 / cy7c65213a usbdp usbdm gnd reset# vcc dcd# dsr# rxd rts# txd cts# dtr# ri# gpio4 gpio5 gpio6 gpio7 gpio0 gpio1 gpio2 gpio3 gnd dcd# dsr# rxd rts# txd cts# dtr# ri# dcdout dsrout rxd rtsout txd ctsout dtrout riout 1 2 3 4 6 7 8 9 5 dcdout dsrout rxdout gnd riout dtrout ctsout txdout rtsout 1k txled# rxled# 1k vccio vccio pwre# sleep# vcc rs232 level converter 4.7 uf 0.1 uf vcc
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 19 of 29 usb to rs485 application cy7c65213a can be configured as usb to uart interface. this uart interface operates at ttl level and it can be converted to rs485 interface using a gpio and any half duplex rs485 transceiver ic (to convert ttl le vel to rs485 level) as shown in following figure1. this gpio (txden) enables and disables the transmission of data through rs485 transceiver ic based on availability of character in uart buffer of cy7c65213a. this gpio can be configured using usb-serial configuration utility. figure 6 shows timing diagram of this gpio. rs485 is a multi-drop network ? that is, many devices can communicate with each other ov er a single two wire cable connection. the rs485 cable requ ires to be terminated at each end of the cable. figure 5. usb to rs485 bridge figure 6. rs485 gpio (txden) timing diagram usb connector vbus d+ d- gnd vccio vccd 1 uf 0.1 uf usb-uart lp cy7c65213a usbdp usbdm gnd reset# vcc txd rxd gpio4 agnd gpio5 gpio6 gpio7 gpio0 gpio1 gpio2 gpio3 gnd gnd dnu dnu dnu dnu dnu dnu txd rxd txdout rxdin 1k txled# rxled# 1k vcc vcc pwre# sleep# vcc rs485 level converter 0.1 uf 0.1 uf vcc txden vcc
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 20 of 29 battery operated bus-powered usb to mcu with battery charge detection figure 7 illustrates cy7c65213/cy7c65213a as a usb-to-microcontroller interface. the txd and rxd lines are used for data transfer, and the rts# and cts# lines are used for handshaking. gpio4 is confi gured as sleep# to indicate to the mcu if the device is in t he usb suspend mode, and the ri# pin is configured to wake up the usb host controller from the suspend mode. this application illustrates a battery-operated system, which is bus-powered. cy7c65213/cy7c65213a implements the battery charger detection functio nality based on the usb battery charging specification rev. 1.2. battery-operated bus power syste ms must comply with the following conditions: 1. the system can be powered from the battery (if not discharged) and can be operational if the vbus is not connected or powered down. 2. the system should not draw more than 100 ma from the vbus prior to usb enumeration and usb suspend. 3. the system should not draw more than 500 ma for sdp and 1.5 a for cdp/dcp. to comply with the first requi rement, the vbus from the usb host is connected to th e battery charger and to cy7c65213/cy7c65213a, as shown in figure 7 . when the vbus is connected, cy7c65213/cy7c65213a initiates battery charger detection and indicate s the type of usb charger over bcd0 and bcd1. if the usb charger is sdp or cdp, cy7c65213/cy7c65213a enables a 1.5-k ? pull-up resistor on the usbdp for full-speed enumeration. when the vbus is disconnected, cy7c65213/cy7c6 5213a indicates an absence of the usb charger over bcd0 and bcd1, and removes the 1.5-k ? pull-up resistor on the usbdp. removing this resistor ensures that no current flows from the supply to the usb host through the usbdp pin, to comply with the usb 2.0 specification. to comply with the second and third requirements, the bcd0 and bcd1 signals are configured over gpio to communicate the type of usb charger and the amount of current the battery charger can draw from the vbus. the bcd0 and bcd1 signals can be configured using th e configuration utility. figure 7. battery-operated bus-powered us b to mcu with battery charge detection [8] bat sys usb connector vbus d+ d- gnd vccio vccd 1 uf usb-uart lp cy7c65213 / cy7c65213a usbdp usbdm gnd reset# txd rxd cts# rts# dtr# dsr# dcd# ri# gpio4 gpio6 gpio7 gpio0 gpio1 gpio2 gpio3 gnd 4.7k bcd0 bcd1 mcu vcc rxd txd rts# cts# i/o gnd i/o sleep# wakeup# gpio5 vcc en2 in battery charger (max8856) en1 4.7k busdetect b a ovp gnd agnd 4.7 uf 0.1 uf vcc note 8. add a 100 k ? pull-down resistor on the vbus pin for quick discharge.
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 21 of 29 in a battery charger system, a 9-v spike on the vbus is possible. the cy7c65213 vcc pin is intolerant to voltage above 6 v. in the absence of over-voltage protection (ovp) on the vbus line, the vbus should be connec ted to busdetect (gpio configured) using the resistive network and the out put of the battery charger to the vcc pin of cy7c65213, as shown in the following figure. figure 8. gpio vbus detect (busdetect) when vbus and vccio are at the same voltage potential, the vbus can be connected to gpio using a series resistor (rs). this is shown in the following figure. if there is a charger failure and the vbus becomes 9 v, then the 10-k ? resistor plays two roles. it reduces the amount of current flowing into the now forward-biased diodes in the gpio, and it reduces the voltage seen on the pad. figure 9. gpio vbus detection, vbus = vccio when vbus > vccio, a resistor voltage divider is required to reduce the voltage from the vbu s down to vccio for the gpio sensing the vbus voltage. this is shown in figure 10 . the resistors should be sized as follows: r1 10 k r2 / (r1 + r2) = vccio / vbus the first condition limits the vo ltage and current for the charger failure situation, as described in the previous paragraph, while the second condition allows for normal-operation vbus detection. figure 10. gpio vbus detection, vbus > vccio led interface any gpio can be configured to drive an led. three configuration options (txled#, rxled#, and tx or rx led#) are available for driving leds. refer to table 13 on page 14 . the following figure shows an exam ple of the cy7c65213 drive single-led configuration a nd dual-led configurations, respectively. in the single-led configuration, the gpio pin is used to indicate when data is transmitted or received over usb by the device (tx or rx led#). in the dual-led configuration, when data is transmitted or received over usb, the respective gpio pins will drive the led to indicate the transfer. figure 11. single-led configuration figure 12. double-led configuration b battery charger bat sys usb-uart lp cy7c65213 / cy7c65213a vcc gpio busdetect rs a b a r1 b a r2 vbus = vccio vbus > vccio r1 = 10 k r2/(r1+r2) = vccio/vbus rs = 10 k vbus rs vbus vccio busdetect cy7c65213 / cy7c65213a r1 vbus r2 vccio cy7c65213 / cy7c65213a busdetect cy7c65213 / cy7c65213a 270r vccio gpio[0..7] tx or rx led# cy7c65213 / cy7c65213a 1k vccio gpio[0..7] gpio[0..7] 1k txled# rxled#
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 22 of 29 ordering information ta b l e 1 4 lists the cy7c65213 key package features and ordering codes. t he table contains only the parts that are currently available. if you do not see what you are seeking, contact your local sale s representative. for more inform ation, visit the cypress websit e at www.cypress.com and refer to the product summary page at http://www.cypress.com/products . ordering code definitions table 14. key features and ordering information package ordering code operating range 28-pin ssop (10 7.5 1.65 mm, 0. 65 mm pitch) cy7c65213-28pvxi industrial 32-pin qfn (5 5 1 mm, 0.5 mm pitc h) (pb-free) cy7c65213-32ltxi industrial 32-pin qfn (5 5 1 mm, 0.5 mm pitch) (pb-free) ? tape and reel cy7c65213-32ltxit industrial 28-pin ssop (10 7.5 1.65 mm, 0.65 mm pitch) CY7C65213A-28PVXI industrial 32-pin qfn (5 5 1 mm, 0.5 mm pitch) (pb-free) cy7c65213a-32ltxi industrial 32-pin qfn (5 5 1 mm, 0.5 mm pitch) (pb-free) ? tape and reel cy7c65213a-32ltxit industrial x = blank or t blank = tube; t = tape and reel temperature range: i = industrial pb-free package type: xx = pv or lt pv = ssop; lt = qfn number of pins: xx = 28 or 32 part number: xxxx = 213 or 213a family code: 65 = usb hubs technology code: c = cmos marketing code: 7 = cypress products company id: cy = cypress c cy 65 i -xx x xxxx 7 xx x
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 23 of 29 package information figure 13. 32-pin qfn (5 5 1.0 mm) lt32b 3. 5 3.5 e-pad (sawn) package outline, 001-30999 figure 14. 28-pin ssop (210 mils) package outline, 51-85079 001-30999 *d 51-85079 *f
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 24 of 29 table 15. package characteristics parameter description min typ max units t a operating ambient temperature ?40 25 85 c thj package ? ja (32-pin qfn) ? 19 ? c/w package ? ja (28-pin ssop) ? 62 ? c/w table 16. solder reflow peak temperature package maximum peak temperature maximum time at peak temperature 32-pin qfn 260 c 30 seconds 28-pin ssop 260 c 30 seconds table 17. package moisture sensitivity level (msl), ipc/jedec j-std-2 package msl 32-pin qfn msl3 28-pin ssop msl3
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 25 of 29 acronyms document conventions units of measure table 18. acronyms used in this document acronym description bcd battery charger detection cdc communication driver class cdp charging downstream port dcp dedicated charging port dll dynamic link library esd electrostatic discharge gpio general-purpose input/output hbm human-body model mcu microcontroller unit osc oscillator phdc personal health care device class pid product identification sdp standard downstream port sie serial interface engine vcom virtual communication port usb universal serial bus uart universal asynchronous receiver transmitter vid vendor identification table 19. units of measure symbol unit of measure ? c degree celsius dmips dhrystone million instructions per second k ? kilo-ohm kb kilobyte khz kilohertz kv kilovolt mbps megabits per second mhz megahertz mm millimeter vvolt
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 26 of 29 document history page document title: cy7c65213/cy7c65213a, usb-uart lp bridge controller document number: 001-81011 revision ecn orig. of change submission date description of change *e 4019327 zkr 06/13/2013 changed status from preliminary to final. *f 4105000 samt 08/26/2013 final prod uction release of datasheet. *g 4250679 mvta 01/17/2014 updated features . updated functional overview : updated description. updated uart interface : updated uart flow control : updated description. updated system resources : updated power system : updated description. updated software : updated windows-ce support : updated description. updated internal flash configuration : updated description. updated table 2 . updated electrical specifications : updated device-level specifications : updated table 4 . updated gpio : updated table 5 . updated pin description : added ta b l e 11 . updated table 12 . updated usb power configuration : updated usb bus-powered configuration : updated figure 1 . updated self-powered configuration : updated figure 2 . updated usb bus powered with variable i/o voltage : updated figure 3 . updated application examples : updated usb to rs232 converter : updated description. added figure 4 . removed the figure ?usb to rs232 converter (32-pin qfn package)?. updated battery operated bus-powered u sb to mcu with battery charge detection : updated description. added figure 7 . removed the figure ?battery-operated bu s-powered usb to mcu with battery charge detection (32-pin qfn package)?. updated ordering information (updated part numbers). updated package information : added figure 14 . updated table 15 , ta b l e 1 6 , table 17 . *h 4287738 samt 02/21/2014 updated ordering information (updated part numbers).
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 27 of 29 *i 4430603 mvta 07/11/2014 updated features . updated functional overview : updated software : updated drivers for windows operating systems : updated description. updated internal flash configuration : updated table 2 : updated details in ?description? column of ?type? parameter. updated electrical specifications : updated device-level specifications : updated table 3 : updated details in ?details/conditions? column of v cc and v ccio parameters. updated typical and maximum values of i cc1 parameter. updated details in ?details/conditions? column of i cc1 parameter. updated usb power configuration : updated usb bus-powered configuration : updated figure 1 . updated self-powered configuration : updated description. updated figure 2 . completing sunset review. *j 4455825 mvta 01/19/2015 added more information . updated package information : spec 51-85079 ? changed revision from *e to *f. updated to new template. *k 4807404 mvta / rrsh 06/23/2015 updated features . updated applications . updated functional overview : updated serial communication : updated uart interface : updated description. updated system resources : updated power system : updated description. updated internal 32-khz oscillator : updated description. updated reset : updated description. updated software : updated drivers for windows operating systems : updated description. updated windows-ce support : updated description. updated electrical specifications : updated operating conditions : updated details corresponding to ?v cc supply voltage?. updated device-level specifications : updated table 3 : changed maximum value of v cc parameter from 5.25 v to 5.5 v. updated gpio : updated table 5 : updated details in ?description? column of v oh and v ol parameters. document history page (continued) document title: cy7c65213/cy7c65213a, usb-uart lp bridge controller document number: 001-81011 revision ecn orig. of change submission date description of change
cy7c65213 cy7c65213a document number: 001-81011 rev. *m page 28 of 29 *k (cont.) 4807404 mvta / rrsh 06/23/2015 updated pin description : updated table 11 : updated details in ?description? column of pin 20. updated table 12 : updated details in ?description? column of pin 19. updated table 13 : added note 5 and referred the same no te in description of ?tristate? gpio configuration option. updated usb power configuration : updated usb bus-powered configuration : updated figure 1 . updated self-powered configuration : updated figure 2 . updated usb bus powered with variable i/o voltage : updated figure 3 . updated application examples : updated usb to rs232 converter : updated figure 4 . updated battery operated bus-powered u sb to mcu with battery charge detection : updated figure 7 . updated to new template. completing sunset review. *l 5063358 mvta 12/24/2015 updated document title to read as ?cy7c65213/cy7c65213a, usb-uart lp bridge controller?. included details of cy7c65213a part number in all instances across the document. updated features : updated description. updated more information : updated description. updated functional overview : updated serial communication : updated uart interface : updated description. updated uart flow control : updated description. updated electrical specifications : updated operating conditions : updated details corresponding to ?v cc supply voltage?. updated device-level specifications : updated table 3 : changed maximum value of v cc parameter from 5.5 v to 5.25 v. updated details in ?details/conditions? column corresponding to i cc2 parameter. updated pin description : updated details in ?description? column corresponding to vcc pin. updated application examples : added usb to rs485 application . updated ordering information : updated part numbers. updated ordering code definitions . *m 5396700 mvta 08/09/2016 added cy7c65213 and cy7c65213-a features comparison . updated the cypress logo and copyright information. updated sales, solutions, and legal information . document history page (continued) document title: cy7c65213/cy7c65213a, usb-uart lp bridge controller document number: 001-81011 revision ecn orig. of change submission date description of change
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